Many electronic circuits use Time-to-Digital Converters (TDCs) to measure the time difference separating two signals, e.g., a start signal and a stop signal, and to provide the time difference in digital form. One exemplary application for a TDC comprises a Radio Frequency (RF) circuit, where a TDC may be used to measure the time difference between a reference signal and an oscillator signal in a Phase-Locked Loop (PLL). TDCs may also be used to detect light/photons in nuclear medical imaging, e.g., Positron Emission Tomography (PET), for Time-Of-Flight (TOF) measurements, e.g., in radiation detection and in laser radars, and in a variety of other space, nuclear, and measurement science applications.
One type of TDC comprises a Charge-to-Digital Timer (CDT). The basic architecture for a conventional CDT comprises a current source, an integrator, and a flash analog-to-digital converter, such as disclosed in “Fast TDC for On-Line TOF Using Monolithic Flash A/D Converter,” J. Dawson, D. Underwood, IEEE Transactions on Nuclear Science, vol. NS-28, no. 1, February 1981. At the time of the Dawson et al. paper, the CDT was implemented using discrete components and a separate flash analog-to-digital converter.
Another exemplary TDC comprises a Vernier Delay Line (VDL), which uses a Complementary Metal-Oxide Semiconductor (CMOS) buffer/inverter delay to measure the time difference between the start and stop signals. By using tapped delay lines, the TDC may achieve resolutions smaller than those achievable with a single inverter delay. For example, a VDL may achieve ˜20 ps resolution with a 65 nm CMOS process.
In general, TDCs used for PLLs rely on delay line based phase quantization. If the delay line is fixed, quantization noise will increase as a function of the output frequency of the oscillator in the PLL. While conventional solutions may adjust the delay line relative to the oscillator output frequency, such efforts typically increase the power dissipation of the PLL as the frequency increases. Increased power dissipation not only reduces the battery life of the device containing the PLL, but it also increases clock interference, which may disturb the operation of the PLL. Further, because delay cells in the delay line create high peak supply currents, it is difficult to maintain the supply voltage of the TDC at a constant level. Variations in the TDC supply voltage modulate the TDC measurement result and cause unwanted modulation of the PLL oscillator. Because the amount of modulation directly depends on the frequency, it is hard to characterize the phase quantization device accurately using conventional calibration techniques.
Thus, there remains a need for improved calibration techniques for TDCs.